The present invention generally relates to chip package reliability monitoring and systems of monitoring, and more particularly to the use of capacitive sensors for 2D, 2.5D, and 3D flip-chip package reliability monitoring.
Flip-chip technology includes methods for interconnecting semiconductor devices, such as integrated circuit (IC) chips to external circuitry using solder bumps that have been deposited onto chip pads. The solder bumps are deposited on the chip pads on a top side of a wafer to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer). The wafer is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is flowed to complete the interconnect. This technique is in contrast to wire bonding, in which the chip is mounted upright, and wires are used to interconnect the chip pads to external circuitry.
In 2D flip-chip packages, chips or die are interconnected on a substrate using flip-chip interconnects and the chips or die are in a side-by-side orientation, i.e. mounted on a single plane. In 3D chip stacks, chips or die are layered on top of one another in a three-dimensional stack with electrical interconnects between layers. This configuration has many benefits, such as providing a designer with the ability to place an increased number of chips in a given two-dimensional area with an increased amount of electrical communications between them. In 2.5D packages, an interconnect substrate known as an interposer is used to provide high density interconnects. The interposer is placed between the substrate and the die, where the interposer has through-silicon vias (TSVs) connecting the metallization layers on its upper and lower surfaces.
Interconnection mechanical failures are a common occurrence within 2D, 2.5D and 3D flip-chip packages. The complex composite (layered/mixed) structure of the packages and associated mismatch in mechanical properties of the various zones, especially coefficient of thermal expansion (CTE), often induce a variety of mechanical failures. One such type of failure is observed at the solder interconnections of Controlled Collapse Chip Connection (C4), where the CTE mismatch between the silicon die and the carrier (e.g. an organic substrate or interposer) leads to failure in those joints. One of the biggest challenges in microelectronics flip-chip packaging is managing/mitigating the chip-packaging interaction (CPI) stresses that occur due to the CTE mismatches. The CTE mismatch between the chip and substrate/interposer creates increased mechanical stress that is highest in the chip corners. CTE mismatch can also drive considerable warpage in the package, which drives mechanical stress on the interconnections and interfill between multiple chips in stacked die, or die on interposers. One method to increase the solder joint life is by encapsulation with underfill, however it does not completely eliminate the possibility of an electrical connection breakage. The underfill is also subject to the high mechanical stresses in the package, and may lead to the development of bulk and interfacial cracks, which propagate into solder interconnections causing failure.
In order to determine the field condition life-cycle for a specific package, strict accelerated reliability testing must be performed. Existing reliability failure analysis techniques are time intensive and costly. Current chip crack propagation confirmation techniques include confocal mode scanning acoustic microscopy (C-SAM), electrical readout and hand probing of C4 nets, and destructive physical failure analysis by cross sectioning the module. Due to the nature of the failure, extensive physical damage to the module and interconnects must be present before C4 net resistance increases to the desired failure criteria and can be detected in the reliability analysis. All three of the above described analysis methods do not provide early failure detection, and do not provide information needed to fully understand the impact of package design on module failure modes and rates. Furthermore, physical failure analysis can find a fail or defect, but not necessarily the defect of interest or the causal defect, because there can be more than one. In addition, these failure and reliability analysis processes are time consuming. Because the route of verifying the fails and root cause physical analysis is lengthy, only a few parts are put through the entire process, thereby limiting the amount of data collected.
There remains a need in the art for a method and system to understand failure progression and sequence in order to develop strategies for stress mitigation and stress design in 2D, 2.5D, and 3D flip-chip packages.